In the design of systems with multiple clock domains, there is a need to transfer information from one clock domain to another. When exchanging transfer data from one clock domain to another several problems emerge, namely metastability and latency.
Metastability: When the two clocks involved in the transfer are independent, the receiving clock domain sees the incoming signal as an asynchronous signal. In this situation, it is necessary to use techniques to ensure the stability of the incoming signal when it is sampled and propagated through the circuit. A typical problem that occurs is when a signal is sampled by a flip-flop triggered by a clock from one domain for sampling data from another clock domain. That is, in the presence of metastability, a flip-flop might not stabilize to a known state within a certain amount of time, thus leading to circuits that produce different results even given the same logic states and inputs. One technique addressing signal stability is the use of synchronizers composed of a chain of flip-flops. Multiple flip-flops are connected together in a chain of a length intended to ensure a required low probability of failure due to metastability.
Latency: When exchanging transfer data from one clock domain to another, a handshaking mechanism is often used to deal with the unpredictability of the transfer time. This handshake is implemented by a pair of signals, one from the sender to the receiver (request) and another from the receiver to the sender (acknowledge). The delay imposed by the handshaking circuitry including the aforementioned chain of flip-flops introduces latency. This latency penalty occurs in each direction and each time transfer data is exchanged between the two clock domains. In some cases the latency for a message (i.e. request and acknowledgement) results in a handshaking latency of four to six cycles or more. In modern systems, a latency of such a magnitude is regarded as a severe timing constraint. In fact, this increased latency may reduce the actual throughput below the generally desired level of one cycle per cross-domain data transfer.
The aforementioned technique of using a chain of flip-flop synchronizers might be acceptable in the special case where the channel (i.e. multiple clock domain exchange circuitry) involved in the data transfers is not in a critical loop of the system, and thus the latency might not impact overall system performance. As an example, a critical loop would exist in the communication between a processing unit and a memory in which addresses are sent from the processing unit to the memory and data are sent from the memory to the processing unit. The loop would be critical if the processing unit would have to halt and wait for the arrival of the data after the address was sent to the memory. Another technique that mitigates the communication latency is the use of asynchronous FIFOs (also called bi-synchronous FIFOs). This technique reduces the latency by decoupling the reading and writing actions since synchronization in only one direction is required (i.e. 2 or 3 cycles to read the “empty” or “full” control signals of the FIFO). Still, crossing clock domains with FIFOs may become a bottleneck in the system if the crossing is in a critical loop.
Asynchronous systems offer new opportunities to implement clock domain crossing mechanisms with reduced latency since the clocks that trigger the sequential elements can be stopped during the normal operation of the circuit. The capability of stopping the clocks enables the use of different techniques to deal with metastability relying on arbitration modules (e.g., mutual exclusion (mutex) elements).
Prior attempts at exchanging transfer data from one clock domain to another clock domain between asynchronous systems have included use of FIFOs designed to work in real-time systems in which the processes for sending and receiving data cannot be blocked for an undefined period of time. To handle the time independence between the reader and the writer, and provide quick response times, mechanisms for addressing the behaviors of data loss and re-reading of old data have been proposed. Such designs use one slot of data storage (e.g. a latch) with a handshaking control to keep track of the validity of the information in the latch. The scheme can be extended to multiple data slots by concatenating them. However, this approach requires arbitration modules (e.g. one or more mutex modules) at the input and also at the output of the FIFO. In the input channel (e.g. for writing), the arbitration separates the request to write from the acknowledgement to accept new data in the FIFO. In the output channel (e.g. for reading), the arbitration separates the request to read from the acknowledgment of data availability in the FIFO. Further highlighting aspects of this approach, this scheme also requires additional latches at the input and at the output of the FIFO.
Designers of electronic systems would prefer only one arbitration module and would prefer designs that do not require latches at the input and output channels.
Moreover, prior proposals have included constraining assumptions and/or egregious limitations that motivate the present disclosure. Thus, it is the advancement of the art and mitigation of the limitations of such prior proposals that motivate the present invention disclosed herein.